The field of the disclosure relates generally to signal processing apparatuses embedding Analog-to-Digital Converters (ADCs) and, more particularly, to methods and systems for determining the Integral Non-Linearity (INL) and consequently the Differential Non-Linearity (DNL) of ADCs.
At least some known signal processing systems trade ADC resolution for speed (or, sampling data rate). This practice however results in an ADC with coarsely quantized transfer functions, whose readings may not be easily calibrated. Prior art solutions for calibrating the ADC rely on methods of extracting the non-linearity to be corrected for, which are based either on: an input signal ramp, which cannot be used for band-pass ADCs; or sinusoidal input signals, whose diverging probability distribution numerically requires disposing of the quantized levels close to the bottom and top of the conversion range (i.e. 25% of all data, if top and bottom levels are discarded for an 8-level 3-bit readings).
More specifically, traditional linearity tests on ADCs are conducted according to a “histogram method”, where a population of digital output codes collected from an ADC stimulated in a known pattern is binned into a histogram with a minimum bin having a width of exactly 1 Least Significant Bit (LSB), and compared to an expected code distribution. The industry standard is a uniform pattern of stimulus to the ADC, i.e., a slow ramp that uniformly exercises every output code of the ADC. In this case, the distribution of the histogram at the ADC output is also supposed to be uniform; therefore, any deviations from uniformity of such histogram are ascribed to the inherent non-linearity of the ADC and characterized as DNL, because each deviation measures an error in the absolute size of each single code, as compared to the theoretical 1-LSB. A running integral of the DNL then yields the INL, which is customarily used in the art to characterize the total distortion introduced by the conversion process.
As stated, using a sequence of DC values, or one or multiple ramps (to speed-up automated testing), is the industry standard and simplifies the static linearity estimation process at large. However, many ADC cores have an inherently band-pass transfer function: due to, for example, an RF front-end preconditioning/amplification that requires AC coupling to remove DC offsets, quasi-DC slow drifts, and/or undesirable slow l/f noise components. This characteristic may prevent the use of the classic DNL/INL testing method.
Moreover, the histogram method construes a histogram containing as many bins as many codes the ADC has. For a 16-bit ADC, e.g., the large population of 216=65,536 bins may constitute an excellent statistical snapshot of the ADC. However, modern global positioning systems (GPS), some communication protocols, and most Radio Detection and Ranging/Light Detection and Ranging (RADAR/LIDAR) systems for aerospace and automotive applications use data-combining techniques from multiple antennas—for example, routed and converted at low-resolution into multiple channels—to maximize the throughput of the whole system. This approach relies on the fast conversion time of simple Flash ADCs with only 3-4 bits each, and often even less. The final outcome of the DNL/INL assessment process as applied to a 3-bit ADC is thus a scant 8-point piece-wise linear plot that is exceedingly difficult to interpret for any localized converter-induced distortion effect.